Fully Integrated CMOS Low-Gain-Wide-Range 2.4 GHz Phase Locked Loop for LR-WPAN Applications

Non

RF CMOS Oscillators Design for autonomous Connected Objects

Voltage controlled oscillator (VCO) is an integral part of IoT wireless transceiver components. In this paper, VCOs operating around 2.4 GHz have been designed in CMOS technology. The relation between their components and specifications is studied for their performance optimization. Ultra-low power, less than 270 µW, has been obtained, while performing a frequency tuning range of about 10% between 2.1 and 2.4 GHz. Investigations on phase noise performance have been also achieved

Test Structure for Ic(Vbe) Parameter Determination of Low Voltage Applications

International audienceThe temperature dependence of the IC(VBE) relationship can be characterised by two parameters: EG and XTI. The classical method to extract these parameters consists in a "best fitting" from measured VBE(T) values, using least square algorithm at constant collector current. This method involves an accurate measurement of VBE voltage and an accurate value of the operating temperature. We propose in this paper, a configurable test structure dedicated to the extraction of temperature dependence of IC(VBE) characteristic for BJT designed with bipolar or BiCMOS processes. This allows a direct measurement of die temperature and consequently an accurate measurement of VBE(T). First, the classical extraction method is explained. Then, the implementation techniques of the new method are discussed, the improvement of the design is presented

Thermal wave variation anticipation under minute scale time-advance with low-pass NGD digital circuit

Over the emerging industry 4.0 era, the building control system performance depends on the development of smart sensor technology. Nowadays, the building control engineers challenge on the design of high-capacity smart sensor susceptible to operate with high speed of data processing. In this context, this paper introduces a pioneer research work on the negative group delay (NGD) circuit original application for room temperature anticipation useful for smart-building control. The real-time anticipation of sensor data by using a low-pass (LP) NGD digital circuit is studied. This approach enables minimizing the latency time for optimizing control action. The unfamiliar LP-NGD digital circuit design method and theoretical formulation are described for anticipating thermal wave experimentation in real-time. The digital circuit equation coefficients are computed regarding the time-advance of anticipated thermal completely arbitrary waveform signal. The main interest of using the NGD method-based for thermal wave anticipation regarding temperature variation from heater and freezer control is demonstrated. The anticipation feasibility is illustrated from the minute scale time-advance LP-NGD digital circuit implemented on the STM32 (R) microcontroller unit. The NGD characterization is performed from frequency domain analysis and cosine waveform pulse transient test. Then, the-30 seconds to-10 seconds real-time-advance of temperature variation is verified by calculation and experimentation. The present study result opens a promising NGD method application for the advanced fault control of a future industrial system by anticipating system failures.Web of Science1012766612765

SITARe: a fast simulation tool for the analysis of disruptive effects on electronics

This paper is devoted to an exhaustive presentation of a fast computation numerical tool, dedicated to the simulation of transient currents induced by stochastic events in microelectronic devices. This is a part of a numerical platform, SITARe, combining a spice simulator with the semi-analytical model presented here. The paper describes the theoretical model, the calibration. An instance of application illustrates the ability of the tool

Influence of triple-well technology on laser fault injection and laser sensor efficiency

International audienceThis study is driven by the need to understand the influence of a Deep-Nwell implant on the sensitivity of integrated circuits to laser-induced fault injections. CMOS technologies can be either dual-well or triple-well. Triple-well technology has several advantages compared to dual-well technology in terms of electrical performances. Single-event responses have been widely studied in dual-well whereas SEE (single event effects) in triple-well is not well understood. This paper presents a comparative analysis of soft error rate and countermeasures sensors with for these two techniques in 40 nm and 90 nm CMOS technology. First, laser fault injection on registers were investigated, showing that triple-well technology is more vulnerable. Similarly, we studied the efficiency of Bulk Built-In Current Sensors (BBICS) in detecting laser induced fault injection attempts for both techniques. This sensor was found less effective in triple-well. Finally, a new BBICS compliant with body-biasing adjustments is proposed in order to improve its detection efficiency

Design method of constant phase-shifter microwave passive integrated circuit in 130-nm BiCMOS technology with bandpass-type negative group delay

The miniaturization and application development are the expected challenges on the today engineering design research on bandpass (BP) type negative group delay (NGD) circuit. To overcome this technical limit, an innovative contribution on integrated circuit (IC) design method of BP-NGD application to design constant phase shifter (PS) in 130-nm BiCMOS technology is developed in the present paper. The BP-NGD PS microwave passive IC is topologically consisted of cascade of CLC- and RLC-resonant networks. After the S-matrix modelling, the synthesis design equations enabling to calculate each lumped component values constituting the BP-NGD PS BiCMOS are established. The design equations are expressed knowing the targeted specifications as phase shift and operating frequency. The BiCMOS design methodology including the key steps as design rule checking (DRC), layout versus schematic (LVS) and post-layout simulation (PLS) is described. The miniaturized BP-NGD PS design feasibility is verified with schematic and layout simulations with IC CMOS standard commercial software tool. A proof-of-concept (POC) of 130-nm BiCMOS BP-NGD PS operating at the center frequency f(0) = 1.9 GHz and bandwidth Delta f = 0.1 GHz is designed and simulated. After DRC, the chip layout of miniaturized BP-NGD PS POC presents 0.407 mm(2) size. The BP-NGD PS POC exhibits constant phase shift notable value of about phi(0) = -90 degrees +/-0.4 degrees under S-21(f(0)) = -6+/-1 dB transmission coefficient with good flatness and reflection coefficients (S-21(f(0)) and S-21(f(0))) widely better than - dB. The design robustness is confirmed by 1000-trial Monte Carlo uncertainty analyses with PLS results. Because of the potential integration in wireless sensor networks (WSNs), the BP-NGD PS under study is a promising candidate for the improvement of the future 5G and 6G transceiver design.Web of Science10931039308

Contribution à l'optimisation de performances des références de tension Bandgap

MONTPELLIER-BU Sciences (341722106) / SudocSudocFranceF

Design of an optimal layout RF passive polyphase filter for large image rejection

International audienc